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ds2250(t) soft microcontroller module ds2250(t) copyright 1995 by dallas semiconductor corporation. all rights reserved. for important information regarding patents and other intellectual property rights, please refer to dallas semiconductor data books. 121395 1/19 features ? 8bit 8051 compatible microcontroller adapts to task athand: 8k, 32k, or 64k bytes of nonvolatile ram for program and/or data memory storage initial downloading of software in end system via onchip serial port capable of modifying its own program and/or data memory in end use ? highreliability operation: maintains all nonvolatile resources for 10 years in the absence of v cc powerfail reset early warning powerfail interrupt watchdog timer ? software security feature: executes encrypted software to prevent unau- thorized disclosure ? onchip, fullduplex serial i/o ports ? two onchip timer/event counters ? 32 parallel i/o lines ? compatible with industry standard 8051 instruction set ? permanently powered real time clock pin assignment 40-pin simm 1202140 description the ds2250(t) soft microcontroller module is a fully 8051 compatible 8bit cmos microcontroller that offers asoftnesso in all aspects of its application. this is ac- complished through the comprehensive use of nonvola- tile technology to preserve all information in the ab- sence of system v cc . the internal program/data memory space is implemented using 8k, 32k, or 64k bytes of nonvolatile cmos sram. furthermore, inter- nal data registers and key configuration registers are also nonvolatile. an optional real time clock gives per- manently powered timekeeping. the clock keeps time to a hundredth of a second using an onboard crystal. all nonvolatile memory and resources are maintained for over 10 years at room temperature in the absence of power.
ds2250(t) 121395 2/19 ordering information part number ram size max crystal speed timekeeping? ds2250816 8k bytes 16 mhz no ds22503216 32k bytes 16 mhz no ds22506416 64k bytes 16 mhz no ds2250t816 8k bytes 16 mhz yes ds2250t3216 32k bytes 16 mhz yes ds2250t6416 64k bytes 16 mhz yes operating information is contained in the user's guide section of the secure microcontroller data book. this data sheet provides ordering information, pinout, and electrical specifications.
ds2250(t) 121395 3/19 ds2250(t) block diagram figure 1 ????? ????? ????? ????? ????? ????? ????? ????? p0.00.7 p1.01.7 p2.02.7 p3.03.7 rst ale psen ea xtal1 xtal2 gnd v cc ds5000fp ??????? ??????? ??????? ??????? ??????? ??????? ??????? ??????? ??????? ??????? ??????? ??????? ??????? ??????? ??????? ??????? ??????? ??????? ??????? ??????? ??????? v cco ce1 r/w ce2 bytewide data bus bytewide address bus +3v 8k or 32k sram real time clock ds2250(t) 32k sram (64 only) (ds2250t)
ds2250(t) 121395 4/19 pin description pin description 1, 3, 5, 7, 9, p1.0 p1.7. general purpose i/o port 1 ,,,,, 11, 13, 15 pp 17 rst active high reset input. a logic 1 applied to this pin will activate a reset state. this pin is pulled down internally so this pin can be left unconnected if not used. an rc poweron reset circuit is not needed and is not recommended. 19 p3.0 rxd. general purpose i/o port pin 3.0. also serves as the receive signal for the on board uart. this pin should not be connected directly to a pc com port. 21 p3.1 txd. general purpose i/o port pin 3.1. also serves as the transmit signal for the on board uart. this pin should not be connected directly to a pc com port. 23 p3.2 int0 . general purpose i/o port pin 3.2. also serves as the active low external interrupt 0. 25 p3.3 int1 . general purpose i/o port pin 3.3. also serves as the active low external interrupt 1. 27 p3.4 t0. general purpose i/o port pin 3.4. also serves as the timer 0 input. 29 p3.5 t1. general purpose i/o port pin 3.5. also serves as the timer 1 input. 31 p3.6 wr . general purpose i/o port pin. also serves as the write strobe for expanded bus operation. 33 p3.7 rd . general purpose i/o port pin. also serves as the read strobe for expanded bus operation. 35, 37 xtal2, xtal1. used to connect an external crystal to the internal oscillator. xtal1 is the input to an inverting amplifier and xtal2 is the output. 39 gnd logic ground. 26, 28, 30, 32, 34, 36, 38, 40 p2.7p2.0. general purpose i/o port 2. also serves as the msb of the expanded address bus. 24 psen program store enable. this active low signal is used to enable an external program memory when using the expanded bus. it is normally an output and should be unconnected if not used. psen also is used to invoke the bootstrap loader. at this time, psen will be pulled down externally. this should only be done once the ds2250(t) is already in a reset state. the device that pulls down should be open drain since it must not interfere with psen under normal operation. 22 ale address latch enable. used to demultiplex the multiplexed expanded address/data bus on port 0. this pin is normally connected to the clock input on a '373 type transparent latch. when using a parallel programmer, this pin also assumes the prog function for pro- gramming pulses. 20 ea external access. this pin forces the ds2250(t) to behave like an 8031. no internal memory (or clock) will be available when this pin is at a logic low. since this pin is pulled down internally, it should be connected to +5v to use nvram. in an parallel programmer, this pin also serves as v pp for super voltage pulses.
ds2250(t) 121395 5/19 pin description 4, 6, 8, 10, 12, 14, 16, 18 p0.0p0.7. general purpose i/o port 0. this port is opendrain and can not drive a logic 1. it requires external pullups. port 0 is also the multiplexed expanded address/data bus. when used in this mode, it does not require pullups. 2 v cc + 5 volts. instruction set the ds2250(t) executes an instruction set which is ob- ject code compatible with the industry standard 8051 microcontroller. as a result, software development packages which have been written for the 8051 are compatible with the ds2250(t), including crossas- semblers, highlevel language compilers, and debug- ging tools. note that the ds2250(t) is functionally iden- tical to the ds5000(t) except for package and the 64k memory option. a complete description for the ds2250(t) instruction set is available in the user's guide section of the secure microcontroller data book. memory organization figure 2 illustrates the address spaces which are ac- cessed by the ds2250(t). as illustrated in the figure, separate address spaces exist for program and data memory. since the basic addressing capability of the machine is 16 bits, a maximum of 64 kbytes of program memory and 64 kbytes of data memory can be ac- cessed by the ds2250(t) cpu. the 8k or 32k byte ram area inside of the ds2250(t) can be used to con- tain both program and data memory. a second 32k ram is available for data only. the realtime clock (rtc) in the ds2250(t) is reached in the memory map by setting a sfr bit. the mcon.2 bit (ece2) is used to select an alternate data memory map. while ece2=1, all movxs will be routed to this alternate memory map. the realtime clock is a serial device that resides in this area. a full description of the rtc access and example software is given in the user's guide section of the secure microcontroller data book.
ds2250(t) 121395 6/19 ds2250(t) memory map figure 2 ffffh 8000h 0000h = nvram memory legend: nvram data 64k nvram data nvram program partition = = ece2=1 ece2=0 program memory 32k expanded bus (ports 0 and 2) not available data memory (movx) program loading the program load modes allow initialization of the nvram program/data memory. this initialization may be performed in one of two ways: 1. serial program loading which is capable of per- forming bootstrap loading of the ds2250(t). this feature allows the loading of the application program to be delayed until the ds2250(t) is installed in the end system. 2. parallel program load cycles which perform the ini- tial loading from parallel address/data information presented on the i/o port pins. this mode is timing set compatible with the 87c51h microcontroller pro- gramming mode. the ds2250(t) is placed in its program load configura- tion by simultaneously applying a logic 1 to the rst pin and forcing the psen line to a logic 0 level. immediately following this action, the ds2250(t) will look for a paral- lel program load pulse, or a serial ascii carriage return (0dh) character received at 9600, 2400, 1200, or 300 bps over the serial port. the hardware configurations used to select these modes of operation are illustrated in figure 3.
ds2250(t) 121395 7/19 program loading configurations figure 3 psen rst d7d0 a15a12 program a7a0 a11a8 program address program control v cc gnd ds2250 p1.7 p1.0 p2.3 p2.0 ea/v pp ale/prog p2.7 p2.6 p2.5 xtal1 xtal2 p0.7 p0.0 p3.7 p3.4 psen rst v cc gnd ds2250 p1.7 p1.0 p2.5 p2.0 xtal1 xtal2 p0.7 p0.0 p3.7 p3.2 11.059 mhz txd rxd drive/ rcv rs232c r<2k address program data in/verify data out r<2k parallel loading serial loading p2.6 p2.7 table 1 summarizes the selection of the available paral- lel program load cycles. the timing associated with these cycles is illustrated in the electrical specs. serial bootstrap loader the serial program load mode is the easiest, fastest, most reliable, and most complete method of initially loading application software into the ds2250(t) nonvol- atile ram. communication can be performed over a standard asynchronous serial communications port. a typical application would use a simple rs232c serial in- terface to program the ds2250(t) as a final production procedure. the hardware configuration which is re- quired for the serial program load mode is illustrated in figure 3. port pins 2.7 and 2.6 must be either open or pulled high to avoid placing the device in a parallel load cycle. although an 11.0592 mhz crystal is shown in fig- ure 3, a variety of crystal frequencies and loader baud rates are supported, shown in table 2. the serial loader is designed to operate across a threewire interface from a standard uart. the receive, transmit, and ground wires are all that are necessary to establish communication with the ds2250(t). the serial bootstrap loader implements an easyto use command line interface which allows an application program in an intel hex representation to be loaded into and read back from the device. intel hex is the typical format which existing 8051 crossassemblers output. the serial loader responds to single character com- mands which are summarized below: command function c return crc16 checksum of em- bedded ram d dump intel hex file f fill embedded ram block with constant k load 40bit encryption key l load intel hex file r read mcon register t trace (echo) incoming intel hex data u clear security lock v verify embedded ram with in- coming intel hex w write mcon register z set security lock p put a value to a port. g get a value from a port.
ds2250(t) 121395 8/19 parallel program load cycles table 1 mode rst psen prog ea p2.7 p2.6 p2.5 program 1 0 0 v pp 10x security set 1 0 0 v pp 11x verify 1 x x 1 0 0 x prog expanded 1 0 0 v pp 010 verify expanded 1 0 1 1 0 1 0 prog mcon or key registers 1 0 0 v pp 011 verify mcon registers 1 0 1 1 0 1 1 the parallel program cycle is used to load a byte of data into a register or memory location within the ds2250(t). the verify cycle is used to read this byte back for comparison with the originally loaded value to verify proper load ing. the security set cycle may be used to enable and the software security feature. one may also enter bytes for the mcon register or for the five encryption registers using the program mcon cycle. when using this cycle, the absolute register ad- dress must be presented at ports 1 and 2 as in the nor- mal program cycle (port 2 should be 00h). the mcon contents can likewise be verified using the verify mcon cycle. when the ds2250(t) first detects a parallel program strobe pulse or a security set strobe pulse while in the program load mode following a power on reset, the internal hardware of the device is initialized so that an existing 4 kbyte program can be programmed into a ds2250(t) with little or no modification. this initializa- tion automatically sets the range address for 8 kbytes and maps the lowest 4 kbyte bank of embedded ram as program memory. the next 4 kbytes of embedded ram are mapped as data memory. in order to program more than 4 kbytes of program code, the program/verify expanded cycles can be used. up to 32 kbytes of program code can be entered and verified. note that the expanded 32 kbyte program/ verify cycles take much longer than the normal 4 kbyte program/verify cycles. a typical parallel loading session would follow this pro- cedure. first, set the contents of the mcon register with the correct range and partition only if using expand- ed programming cycles. next, the encryption registers can be loaded to enable encryption of the program/data memory (not required). then, program the ds2250(t) using either normal or expanded program cycles and check the memory contents using verify cycles. the last operation would be to turn on the security lock fea- ture by either a security set cycle or by explicitly writing to the mcon register and setting mcon.0 to a 1.
ds2250(t) 121395 9/19 serial loader baud rates for different crystal frequencies table 2 crystal freq (mhz) baud rate crystal freq (mhz) 300 1200 2400 9600 19200 57600 14.7456 y y y y 11.0592 y y y y y y 9.21600 y y y y 7.37280 y y y y 5.52960 y y y y 1.84320 y y y y additional information a complete description for all operational aspects of the ds2250(t) is provided in the user's guide section of the secure microcontroller data book. development support dallas semiconductor offers a kit package for develop- ing and testing user code. the ds5000tk evaluation kit allows the user to download intel hex formatted code directly to the ds2250(t) from a pcxt/at or compat- ible computer. the kit consists of a ds5000t3212, an interface pod, demo software, and an rs232 con- nector that attaches to the com1 or com2 serial port of a pc. the kit can be used with a ds2250(t). a mechan- ical adaptor, the ds907540v, allows a ds2250(t) to be used in the ds5000tk. see the secure microcon- troller user's guide for further details.
ds2250(t) 121395 10/19 absolute maximum ratings* voltage on any pin relative to ground 0.3v to +7.0v operating temperature 0 c to 70 c storage temperature 40 c to +70 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc characteristics (t a = 0 c to70 c; v cc = 5v + 5%) parameter symbol min typ max units notes input low voltage v il 0.3 +0.8 v 1 input high voltage v ih1 2.0 v cc +0.3 v 1 input high voltage rst, xtal1 v ih2 3.5 v cc +0.3 v 1 output low voltage @ i ol =1.6 ma (ports 1, 2, 3) v ol1 0.15 0.45 v output low voltage @ i ol =3.2 ma (ports 0, ale, psen ) v ol2 0.15 0.45 v 1 output high voltage @ i oh =80 m a(ports 1, 2, 3) v oh1 2.4 4.8 v 1 output high voltage @i oh =400 m a(ports 0, ale, psen ) v oh2 2.4 4.8 v 1 input low current v in = 0.45v (ports 1, 2, 3) i il 50 m a transition current; 1 to 0 v in = 2.0v (ports 1, 2, 3) i tl 500 m a input leakage current 0.45 < v in < v cc (port 0) i l + 10 m a rst, ea pulldown resistor r re 40 125 k w stop mode current i sm 80 m a 4 power fail warning voltage v pfw 4.15 4.6 4.75 v 1 minimum operating voltage v ccmin 4.05 4.5 4.65 v 1 programming supply voltage (parallel program mode) v pp 12.5 13 v 1 program supply current i pp 15 20 ma operating current ds22508k ds225032k @ 12 mhz ds2250(t)6416 @ 16 mhz i cc 43 48 54 ma 2 idle mode current @ 8 mhz i cc 6.2 ma 3
ds2250(t) 121395 11/19 ac characteristics expanded bus mode timing specifications (t a = 0 c to70 c; v cc = 5v + 5%) # parameter symbol min max units 1 oscillator frequency 1/t clk 1.0 16 (16) mhz 2 ale pulse width t alpw 2t clk 40 ns 3 address valid to ale low t avall t clk 40 ns 4 address hold after ale low t avaav t clk 35 ns 5 ale low to valid instr. in @12 mhz @16 mhz t allvi 4t clk 150 4t clk 90 ns 6 ale low to psen low t allpsl t clk 25 ns 7 psen pulse width t pspw 3t clk 35 ns 8 psen low to valid instr. in @12 mhz @16 mhz t pslvi 3t clk 150 3t clk 90 ns ns 9 input instr. hold after psen going high t psiv 0 ns 10 input instr. float after psen going high t psix t clk 20 ns 11 address hold after psen going high t psav t clk 8 ns 12 address valid to valid instr. in @12 mhz @16 mhz t avvi 5t clk 150 5t clk 90 ns ns 13 psen low to address float t pslaz 0 ns 14 rd pulse width t rdpw 6t clk 100 ns 15 wr pulse width t wrpw 6t clk 100 ns 16 rd low to valid data in @12 mhz @16 mhz t rdldv 5t clk 165 5t clk 105 ns ns 17 data hold after rd high t rdhdv 0 ns 18 data float after rd high t rdhdz 2t clk 70 ns 19 ale low to valid data in @12 mhz @16 mhz t allvd 8 clk 150 8t clk 90 ns ns 20 valid addr. to valid data in @12 mhz @16 mhz t avdv 9t clk 165 9t clk 105 ns ns 21 ale low to rd or wr low t allrdl 3t clk 50 3t clk +50 ns 22 address valid to rd or wr low t avrdl 4t clk 130 ns 23 data valid to wr going low t dvwrl t clk 60 ns 24 data valid to wr high @12 mhz @16 mhz t dvwrh 7t clk 150 7t clk 90 ns ns 25 data valid after wr high t wrhdv t clk 50 ns 26 rd low to address float t rdlaz 0 ns 27 rd or wr high to ale high t rdhalh t clk 40 t clk +50 ns
psen 27 19 21 14 16 26 4 3 22 20 17 18 ale port 0 port 2 p2.7p2.0 or a15a8 from dph a15a8 from pch data in instr in a7a0 (pcl) a7a0 (rn or dpl) rd ds2250(t) 121395 12/19 expanded program memory read cycle 2 6 7 5 8 11 10 9 12 3 4 13 ale psen port 0 port 2 a7a0 a15a8 instr in a7a0 a15a8 expanded data memory read cycle
ds2250(t) 121395 13/19 expanded data memory write cycle 27 21 15 23 3 4 24 25 22 ale port 0 port 2 wr psen data out a7a0 (rn or dpl) a7a0 (pcl) instr in p2.7p2.0 or a15a8 from dph a15a8 from pch external clock timing 28 29 30 31 1
ds2250(t) 121395 14/19 ac characteristics (cont'd) external clock drive (t a = 0 c to70 c; v cc = 5v + 5%) # parameter symbol min max units 28 external clock high time @12 mhz @16 mhz t clkhpw 20 15 ns ns 29 external clock low time @12 mhz @16 mhz t clklpw 20 15 ns ns 30 external clock rise time @12 mhz @16 mhz t clkr 20 15 ns ns 31 external clock fall time @12 mhz @16 mhz t clkf 20 15 ns ns ac characteristics (cont'd) power cycling timing (t a = 0 c to70 c; v cc = 5v + 5%) # parameter symbol min max units 32 slew rate from v ccmin to 3.3v t f 40 m s 33 crystal start up time t csu (note 5) 34 power on reset delay t por 21504 t clk serial port timing mode 0 instruction 012345678 ale clock data out input data 01234567 35 37 36 39 38 set ti set ri valid valid valid valid valid valid valid clear ri write to sbuf register
ds2250(t) 121395 15/19 ac characteristics (cont'd) serial port timing mode 0 (t a = 0 c to70 c; v cc = 5v + 5%) # parameter symbol min max units 35 serial port cycle time t spclk 12t clk m s 36 output data setup to rising clock edge t doch 10t clk 133 ns 37 output data hold after rising clock edge t chdo 2t clk 117 ns 38 clock rising edge to input data valid t chdv 10t clk 133 ns 39 input data hold after rising clock edge t chdiv 0 ns power cycle timing v cc v pfw v ccmin v li interrupt service routine clock osc internal reset lithium current 32 33 34
ds2250(t) 121395 16/19 ac characteristics (cont'd) parallel program load timing (t a = 0 c to70 c; v cc = 5v + 5%) # parameter symbol min max units 40 oscillator frequency 1/t clk 1.0 12.0 mhz 41 address setup to prog low t avprl 0 42 address hold after prog high t prhav 0 43 data setup to prog low t dvprl 0 44 data hold after prog high t prhdv 0 45 p2.7, 2.6, 2.5 setup to v pp t p27hvp 0 46 v pp setup to prog low t vphprl 0 47 v pp hold after prog low t prhvpl 0 48 prog width low t prw 2400 t clk 49 data output from address valid t avdv 48 1800* t clk 50 data output from p2.7 low t dvp27l 48 1800* t clk 51 data float after p2.7 high t p27hdz 0 48 1800* t clk 52 delay to reset/psen active after power on t porpv 21504 t clk 53 reset/psen active (or verify inactive) to v pp high t ravph 1200 t clk 54 v pp inactive (between program cycles) t vpppc 1200 t clk 55 verify active time t vft 48 2400* t clk * second set of numbers refers to expanded memory programming up to 32k bytes.
ds2250(t) 121395 17/19 parallel program load timing address address address p2.3p2.0 p1.7p1.0 port ale/prog v ih v pp ea/v pp p2.7, p2.6, p2.5 active data data data +5v v cc rst psen 49 51 42 41 43 44 54 48 47 46 45 52 53 55 50 53 capacitance (test frequency = 1 mhz; t a = 25 c) parameter symbol min typ max units notes output capacitance c o 10 pf input capacitance c i 10 pf
ds2250(t) 121395 18/19 ds2250(t) typical i cc vs. frequency icc current (ma) 30.0 25.0 20.0 15.0 10.0 5.0 0 0.0 5.0 10.0 15.0 normal operation idle mode operation frequency of operation (mhz) (v cc =+5v, t a =25 c) normal operation is measured using: 1) external crystals on xtal1 and 2 2) all port pins disconnected 3) rst=0 volts and ea=v cc 4) part performing endless loop writing to internal memory. idle mode operation is measured using: 1) external clock source at xtal1; xtal2 floating 2) all port pins disconnected 3) rst=0 volts and ea=v cc 4) part set in idle mode by software. notes: 1. all voltages are referenced to ground. 2. maximum operating i cc is measured with all output pins disconnected; xtal1 driven with t clkr , t clkf =10 ns, v il = 0.5v; xtal2 disconnected; ea = rst = port0 = v cc . 3. idle mode i cc is measured with all output pins disconnected; xtal1 driven at 8 mhz with t clkr , t clkf = 10 ns, v il = 0.5v; xtal2 disconnected; ea = port0 = v cc , rst = v ss . 4. stop mode i cc is measured with all output pins disconnected; ea = port0 = v cc ; xtal2 not connected; rst = v ss . 5. crystal start up time is the time required to get the mass of the crystal into vibrational motion from the time that power is first applied to the circuit until the first clock pulse is produced by the on-chip oscillator. the user should check with the crystal vendor for the worst case spec on this time.
f (side a) (side b) a c g c l d e i i k l h m j o n p b (side b) ds2250(t) 121395 19/19 package drawing pkg 40pin dim min max a 2.645 2.655 b 2.379 2.389 c 0.845 0.855 d 0.395 0.405 e 0.245 0.255 f 0.050 bsc g 0.075 0.085 h 0.245 0.255 i 0.950 bsc j 0.120 0.130 k 1.320 1.330 l 1.445 1.455 m 0.057 0.067 n 0.160 o 0.195 p 0.054

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